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PDK

PDKProcess Design Kit

An Optimal Design Solution for High-Quality Semiconductor Development

DB HiTek’s PDK (Process Design Kit) includes all the foundry data and related resources necessary for chip design. It allows designers to efficiently carry out the entire design flow, from schematic and layout design to verification and tape-out, with ease and convenience.

Design Flow PDK
  1. Schematic Design
    Defines the functional design of the schematic diagram.
    PDKSymbols
    Provides symbols for schematic components such as transistors and resistors, including PMOS, NMOS, BJT, and RES.
  2. Pre-layout Simulation
    Circuit behavior is verified through pre-layout simulation.
    PDKSPICE* Model
    Provides SPICE models to accurately predict the electrical behavior of each device. * SPICE : Simulation Program with Integrated Circuit Emphasis
  3. Layout Design
    Creates the physical layout of the circuit.
    PDKPCells
    Automates repetitive layout generation using parameterized cells, including PMOS, NMOS, and BJT.
  4. Verification & Parasitic Extraction
    Verifies design rule compliance through DRC, LVS, and LPE processes.
    PDKRuledecks
    Provides rule files for DRC and LVS, as well as files for extracting parasitic elements between devices and interconnects.
  5. Post-layout Simulation
    Verifies final circuit performance after layout implementation.
    PDKSPICE Model + LPE*
    Provides simulations that incorporate SPICE models and parasitic characteristics. * LPE : Layout Parasitic Extraction

Platforms

DB HiTek provides a variety of PDKs that work seamlessly with major EDA tools during the circuit design process.

EDA* Tool * EDA : Electronic Design Automation
PDK
Components
SPICE SPECTRE HSPICE
Symbol/Pcell Virtuoso Tanner Custom
Compiler		 Aether ADS
w/Virtuoso
Ruledecks PVS/
Assura QRC		 Calibre DRC/
LVS xRC		 ICV StarRC
EM Tech Voltus-xFi Totem

  • Provides a variety of user-friendly utilities, from installation to circuit design, simulation, and layout

  • Supports customized compilers and environments such as Empyrean and Tanner EDA through iPDKs for specific processes

  • Enables compatibility between different PDKs (e.g., Keysight ADS PDK and Cadence Virtuoso PDK) for specific design flows

  • Delivers accurate process information and precise SPICE models

  • Supports modeling and simulation through a wide range of features

  • Broadly supports general-purpose device characteristics

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